1. Field of the Invention
The present invention relates generally to techniques for designing and optimizing semiconductor devices and, in particular, to automated techniques for substituting low threshold voltage transistor, gate, or cell instances in a semiconductor design.
2. Description of the Related Art
Integrated circuit designers may replace standard threshold voltage (Vt) transistors with low Vt transistors in critical circuit paths to increase clock speeds of high-speed circuits while meeting semiconductor device process limitations. In general, low Vt transistors have a reduced intrinsic delay as compared to corresponding standard Vt cells. As a result, use of a low Vt cell instance in substitution for a cell instance that contributes to a maximum time violation in a timing path may allow an integrated circuit design to operate at a higher frequency. However, under some circumstances, low Vt cells may exhibit increased intrinsic delays as compared to standard Vt cells. For example, devices manufactured using one process technology may exhibit an increase in the intrinsic delay of a low Vt cell as compared to a standard Vt counterpart for falling edge transitions at the inputs of higher fan-in cells. Accordingly, there is a need for a technique that identifies these low Vt cells that reduce performance as compared to standard Vt cells, and selectively replaces these low Vt cells with standard Vt cells to improve circuit performance.